1. Technical Field
The present invention relates to memory circuits in general, and in particular to static random access memory circuits. Still more particularly, the present invention relates to a sense amplifier circuit for static random access memory circuits.
2. Description of Related Art
In general, memory cells within a static random access memory (SRAM) are connected to a set of bitline pairs BL and *BL. Each of the memory cells is also connected to a wordline WL disposed in the direction perpendicular to the bitline pairs. The data in each of the memory cells appears as an extremely small voltage difference between the corresponding bitline pair connected to the memory cell. Such voltage difference is typically in the range of several tens of a millivolt, and a sense amplifier is commonly utilized to differentially amplify the small voltage difference.
Referring now to the drawings and in particular to FIG. 1, there is depicted a circuit diagram of a sense amplifier according to the prior art. As shown, a latch-type sense amplifier 10 includes p-channel transistors 11-12 and n-channel transistors 13-15. A small potential difference between a bitline pair BL and *BL is sent to output nodes OUT and *OUT via transistors 13 and 14, respectively. When the logic level of BL is high while the logic level of *BL is low, transistor 13 eventually turns on and transistor 15 turns off. Thus, a logic high voltage appears at the output node on the Vcc side of transistor 14, and a logic low voltage appears at the output node on the Vcc side of transistor 13. Such voltage difference is positively fed back by transistors 11 and 12, and is sent to the output nodes OUT and *OUT as complementary signals. When sense amplifier 10 outputs the complementary signals, an enable signal having a voltage equal to the power supply voltage Vcc is applied to the gate of transistor 15 to maintain transistor 15 being turned on.
Conventional sense amplifiers, such as latch-type sense amplifier 10, tend to be relatively slow because the bitline pair BL and *BL has a relatively large capacitive load, depending on the array size. Such relative high capacitive load hinders the development of a sufficiently acceptable differential signal between BL and *BL. Consequently, it would be desirable to provide a sense amplifier circuit that can operate in a relatively high speed.